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1 ? fn7360.4 el7554 monolithic 4 amp dc-dc step-down regulator the el7554 is a full-feature synchronous 4a step-down regulator capable of up to 96% efficiency. this device operates from 3v to 6v v in input supply. with internal cmos power fets, the device can operate at up to 100% duty ratio, allowing for output voltage range from 0.8v up to nearly v in .the adjustable high switching frequency of up to 1mhz enables the use of sm all components, making the whole converter occupy less than 0.58 square inch with components on one side of the pcb. the el7554 operates at constant frequency pwm mode, making external synchronization possible. the el7554 features soft-start and full start-up control, which eliminates the in-rush current and enables users to control the start-up of multiple converters to any configurat ion with ease. the el7554 also offers a 5% voltage margining capability that allows raising and lowering of the supplies derived from the el7554 to validate the perfo rmance and reliabilit y of system cards quickly and easily during manufacturing testing. a junction temperature indicator convenient ly monitors the silicon die temperature, saving designers time in the tedious thermal characterization. an easy-to-use simulation tool is available for download and can be used to modify design pa rameters such as switching frequency, voltage ripple, ambient temperature, as well as view schematics waveforms, efficiency graphs, and complete bom with gerber layout. the el7554 is available in a 28 ld htssop package and is specified for operation over th e -40c to +85c temperature range. features ? integrated mosfets ? 4a continuous output current ? up to 96% efficiency ? all ceramic capacitors ? multiple supply start-up tracking ? built-in 5% voltage margining ? 3v to 6v input voltage ? 0.58 in 2 footprint with components on one side of pcb ? adjustable switching frequency to 1mhz ? oscillator synchronization possible ? 100% duty ratio ? junction temperature indicator ? over-temperature protection ? internal soft-start ? variable output voltage down to 0.8v ? power-good indicator ? 28 ld htssop package ? pb-free plus anneal available (rohs compliant) applications ? point-of-regulation power supplies ? fpga core and i/o supplies ? dsp, cpu core, and io supplies ? logic/bus supplies ? portable equipment related documentation ? technical brief 418 - using the el7554 demo board ? easy to use applications software simulation tool available at www.intersil.com/dc-dc ordering information part number part marking tape & reel package pkg. dwg. # el7554ire 7554ire - 28 ld htssop mdp0048 el7554ire-t7 7554ire 7? 28 ld htssop mdp0048 el7554ire-t13 7554ire 13? 28 ld htssop mdp0048 el7554irez (see note) 7554irez - 28 ld htssop (pb-free) mdp0048 el7554irez-t7 (see note) 7554irez 7? 28 ld htssop (pb-free) mdp0048 EL7554IREZ-T13 (see note) 7554irez 13? 28 ld htssop (pb-free) mdp0048 note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. inters il pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet may 8, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2004-2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn7360.4 may 8, 2006 typical application diagram 0.018f 0.018f 2.2h 47f v out (1.8v, 4a) 2x10f v in (3v to 6v) 0.22f 220pf comp vref fb vo vtj tm sel lx lx lx lx lx lx nc sgnd cosc stn stp en pg vdd vin vin vin pgnd pgnd pgnd nc 1 2 3 4 28 27 26 25 5 6 7 24 23 22 8 21 9 10 20 19 11 12 13 18 17 16 14 15 r 2 r 1 2.32k 10.2k 12.7k c c r c c out c osc c in el7554
3 fn7360.4 may 8, 2006 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maxi mum ratings (t a = 25c) v in , v dd to sgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v vx to pgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v in +0.3v sgnd to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v comp, v ref , fb, v o , v tj , tm, sel, pg, en, stp, stn, c osc to sgnd . . . . . -0.3v to v dd +0.3v storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. dc electrical specifications v dd = v in = 3.3v, t a = t j = 25c, c osc = 390pf, unless otherwise specified parameter description conditions min typ max unit v in input voltage range 3 6 v v ref reference accuracy 1.24 1.26 1.28 v v reftc reference temperature coefficient 50 ppm/c v refload reference load regulation 0 < i ref < 50a -1 % v ramp oscillator ramp amplitude 1.15 v i osc_chg oscillator charge current 0.1v < v osc < 1.25v 200 a i osc_dis oscillator discharge current 0.1v < v osc < 1.25v 8 ma i vdd v dd supply current v en = 1 (l disconnected) 2 2.7 5 ma i vdd_off v dd standby current en = 0 1 1.5 ma v dd_off v dd for shutdown 2.4 2.65 v v dd_on v dd for startup 2.6 2.95 v t ot over-temperature threshold 135 c t hys over-temperature hysteresis 20 c i leak internal fet leakage current en = 0, l x = 6v (low fet), l x = 0v (high fet) 10 a i lmax peak current limit 6a r dson1 pfet on resistance 35 70 m r dsontc2 nfet on resistance 30 60 m r dsontc r dson te m p c o 0.2 m /c i stp stp pin input pull-down current v stp = v in /2 -4 2.5 a i stn stn pin input pull-up current v stn = v in /2 2.5 4 a v pgp positive power good threshold with respect to target output voltage 6 14 % v pgn negative power good threshold with respect to target output voltage -14 -6 % v pg_hi power good drive high i pg = 1ma 2.6 v v pg_lo power good drive low i pg = -1ma 0.5 v v ovp output over-voltage protection 10 % v fb output initial accuracy i load = 0a 0.79 0.8 0.81 v v fb_line output line regulation v in = 3.3v, v in = 10%, i load = 0a 0.2 0.5 % gm ea error amplifier transconductance v cc = 0.65v 85 125 165 s v fb_tc output temperature stability 0c < t a < 85c, i load = 3a 1 % f s switching frequency 300 370 440 khz i fb feedback input pull-up current v fb = 0v 100 200 na el7554
4 fn7360.4 may 8, 2006 v en_hi en input high level 2.6 v v en_lo en input low level 1v i en enable pull-up current v en = 0 -4 -2.5 a tm, s el_hi input high level 2.6 v tm, s el_lo input low level 1v dc electrical specifications v dd = v in = 3.3v, t a = t j = 25c, c osc = 390pf, unless otherwise specified parameter description conditions min typ max unit pin descriptions pin number pin name pin function 1 comp error amplifier output; place loop compensation components here 2 vref bandgap reference bypass capacitor; typically 0.01f to 0.047f to sgnd 3 fb voltage feedback input; connected to external resistor divider between v out and sgnd for adjustable output; also used for speed-up capacitor connection 4 vo output sense for fixed output; also used for speed-up capacitor connection 5 vtj junction temperature monitor output, connected to a 0.01f - 0.047f to sgnd 6 tm stress test enable; allows 5% output movemen t; needs a pull-down resistor (1k - 100k); connect to sgnd if function is not used 7 sel positive or negative voltage margining set pin; needs a pull-down resistor (1k - 100k); connect to sgnd if function is not used 8, 9, 10, 11, 12, 13 lx inductor drive pin; high current output whose average voltage equals the regulator output voltage 14, 15 nc not used 16, 17, 18 pgnd ground return of the regulator; connected to the source of the low-side synchronous nmos power fet 19, 20, 21 vin power supply input of the regulator; conne cted to the drain of the high-side pmos power fet 22 vdd control circuit posit ive supply; connected to v in through an internal 20 resistor 23 pg power-good window comparator output; logic 1 when regulator output is within 10% of target output voltage 24 en chip enable, active high; a 2a internal pull-up current enables the device if the pin is left open; a capacitor can be added at this pin to delay the start of a converter 25 stp auxilliary supply tracki ng positive input; tied to regulator output to synchronize start-up with a second supply; leave open for standalone operatio n; 2a internal pull-up current 26 stn auxiliary supply tracking negativ e input; connect to output of a second supply to synchronize start-up; leave open for standalone operation; 2a internal pull-up current 27 cosc oscillator timing capa citor (see performance curves) 28 sgnd control circuit negative supply or signal ground el7554
5 fn7360.4 may 8, 2006 block diagram drivers pwm controller power tracking current sense voltage reference oscillator 2.2nf stp stn sgnd power power fet fet 220pf 0.018f 2.2h v out (up to 4a) 47f v ref c osc pgnd v tj fb en - + pg v ref v in v in v dd 2x10f v o r 2 v dd tm sel 20 ea comp 0.22f v dd r 1 r c c c junction temperature el7554
6 fn7360.4 may 8, 2006 typical performance curves v in = v d = 3.3v, v o = 1.8v, i o = 4a, l = 2.2h, c in = 2x10f, c out = 47f, c osc = 220pf, t a = 25c unless otherwise noted. figure 1. efficiency (v in = 5v) figure 2. efficiency (v in = 3.3v) figure 3. v ref vs temperature figure 4. v tj vs temperature figure 5. v en_hi & v en_low vs v dd figure 6. f s vs c osc 1 0.7 0.65 0.6 01 4 efficiency (%) i o (ma) 0.9 v o =3.3v 0.8 0.85 23 v o =2.5v v o =0.8v v o =1v v o =1.2v v o =1.8v 0.75 0.95 100 70 65 60 01 4 efficiency (%) i o (ma) 90 v o =2.5v 80 85 23 v o =0.8v v o =1v v o =1.2v v o =1.8v 75 95 1.266 1.25 1.246 -50 150 v ref junction temperature 1.254 50 1.258 1.262 0 100 v dd =3.3v v dd =5v 1.248 1.252 1.256 1.26 1.264 1.6 0.9 -50 150 v tj junction temperature 1.2 50 0 100 v dd =3.3v v dd =5v 1 1.1 1.3 1.4 1.5 4 2 1.5 1 3456 v dd (v) 3.5 v en_hi v en_low 2.5 3 3.5 4.5 5.5 1200 500 200 0 100 300 500 700 f s (khz) c osc (pf) 1000 v dd =3.3v v dd =5v 600 800 200 400 600 el7554
7 fn7360.4 may 8, 2006 figure 7. f s vs i o figure 8. load regulations figure 9. htssop thermal resistance vs pcb area (no air flow) figure 10. package power dissipation vs ambient temperature figure 11. package power dissipation vs ambient temperature typical performance curves (continued) v in = v d = 3.3v, v o = 1.8v, i o = 4a, l = 2.2h, c in = 2x10f, c out = 47f, c osc = 220pf, t a = 25c unless otherwise noted. 610 590 585 01.52.54 f s (khz) i o (a) 595 0.5 2 3.5 600 605 1 3 v in =5v v in =3.3v 0.8 -0.2 -0.4 04 (%) i o (a) 0.6 0.2 123 0.4 0.0 50 45 40 35 30 25 123456789 pcb area (in 2 ) ja (c/w) condition: 28 ld htssop thermal pad soldered to 2-layer pcb with 0.039" thickness and 1 oz. copper on both sides jedec jesd51-7 high effective thermal conductivity test board 3.5 2.5 2.0 1.0 0.5 0 0 25 50 75 100 150 ambient temperature (c) allowable power dissipation (w) 125 85 1.5 j a = 3 0 c / w h t s s o p 2 8 3.0 1.00 0.90 0.30 0 0 255075100 150 ambient temperature (c) allowable power dissipation (w) 85 j a = 1 1 0 c / w h t s s o p 2 8 0.70 0.20 0.50 125 jedec jesd51-3 low effective thermal conductivity test board 0.10 0.40 0.60 0.80 el7554
8 fn7360.4 may 8, 2006 waveforms v in = v d = 3.3v, v o = 1.8v, i o = 4a, l = 2.2h, c in = 2x10f, c out = 47f, c osc = 220pf, t a = 25c unless otherwise noted. figure 12. start-up figure 13. steady-state operation figure 14. shut-down fig ure 15. transient response figure 16. voltage margining figure 17. over-voltage shut-down v in (2v/div) i in (1a/div) v o (1v/div) pg (2v/div) 0.5ms/div v in (100mv/div) v lx (2v/div) v o (10mv/div) 1s/div v en i in (2a/div) v o (2v/div) 50s/div 3a i o v o (100mv/div) 1.0a 100s/div tm sel v o (200mv/div) 1ms/div pg v o (2v/div) v lx (5v/div) 0.5ms/div el7554
9 fn7360.4 may 8, 2006 detailed description the el7554 is a full-feature synchronous 6a step-down regulator capable of up to 96% efficiency. this device operates from 3v to 6v v in input supply. with internal cmos power fets, the device can operate at up to 100% duty ratio, allowing for output voltage range from 0.8v up to nearly v in .the adjustable high switching frequency of up to 1mhz enables the use of sm all components, making the whole converter occupy less than 0.58 square inch with components on one side of the pcb. the el7554 operates at constant frequency pwm mode, making external synchronization possible. patented on-chip resistorless current-sensing enables curr ent mode control, which provides over-current protec tion, and excellent step load response. the el7554 features soft-start and full start-up control, which eliminate the in-rush current and enables users to control the start-up of multiple converters to any configuration with ease. the el7554 also offers a 5% voltage margining capability that allows raising and lowering of the supplies derived from the el7554 to validate the performance and reliability of system cards quickly and easily during manufacturing testing. a junction temperature indicator conveniently monitors the silicon die temperature, saving designers time in the tedious thermal characterization. start-up the el7554 employs a special soft-start to suppress the in- rush current (see figure 12). the start-up process takes about 2ms and begins when the input voltage reaches about 2.8v and en pin voltage 2v. when en is released from low, or the converter comes out of thermal shut-down mode, the soft-start process repeats. when the input voltage ramps up too slowly, slight over- current at the input can occur. connecting a small capacitor at en will delay the start-up. the delay time t d can be calculated by: where: ?c en is the capacitance at en pin ?v en_hi is the en input high level (function of v dd voltage, see figure 5) ?i en is the en pin pull-up current, nominal 2.5a if a slower than 2ms soft start-up is needed, please refer to full start-up control section. steady-state operation the converter always operates at fixed frequency continuous-conduction mode. for fast transient response, peak current control method is employed. the inductor current is sensed from the upper pfet. this current signal, the slope compensation, and the compensated error signal are fed to the pwm comparator to generate the pwm signal for the internal power switches . when the upper pfet is on, the low-side nfet is off and input voltage charges the inductor. when pfet is off, the nfet is on and energy stored in the inductor is dum ped to the output to maintain constant output voltage. ther efore, the lx waveform is always a stable square waveform (see figure 13) with peak close to v in . so lx is a good indicati on that the converter is operating properly. 100% duty ratio el7554 uses cmos as internal synchronous power switches. the upper switch is a pmos and the lower switch an nmos. this not only saves a boot capacitor, it also allows 100% turn-on of the upper pfet switch, achieving figure 18. adjustable start-up figure 19. tracking start-up waveforms (continued) v in = v d = 3.3v, v o = 1.8v, i o = 4a, l = 2.2h, c in = 2x10f, c out = 47f, c osc = 220pf, t a = 25c unless otherwise noted. v in (2v/div) i in (2a/div) v o (1v/div) 2ms/div c in = 100f, c out = 150f v in (5v/div) v o1 =2.5v v o2 =1.8v 5ms/div c in = 100f, c out = 150f t d c en v en_hi i en -------------------- = el7554
10 fn7360.4 may 8, 2006 v o close to v in . the maximum achievable v o is: where r l is the dc resistance on the inductor and r dson1 is the pfet on-resistance, nominal 35m at room temperature with tempco of 0.2m /c. output voltage selection the output voltage can be as high as the input voltage minus the pmos and inductor voltage drops. use r 1 and r 2 to set the output voltage according to the following formula: standard values of r 1 and r 2 are listed in table 1. voltage margining the el7554 has built-in 5% load stress test (commonly called voltage margining) function. combinations of tm and sel set the margins shown in table 2. when this function is not used, both pins should be connected to sgnd, either directly or through a 10k resister. figure 16 shows this feature. switching frequency the regulator operates from 200khz to 1mhz. the switching frequency is generated by a relaxation comparator and adjusted by a c osc . the triangle waveform has 95% duty ratio and runs from 0.2v to 1.2v. please refer to figure 6 for a specific frequency. when external synchronization is required, use the following circuit for connection. always choose the converter self- switching frequency 20% lower than the sync frequency to accommodate component variations. figure 20. external sync circuit thermal protection and junction temperature indicator an internal temperature sensor continuously monitors the junction temperature. in the event that the junction temperature exceeds 135c, the regulator is in a fault condition and will shut down. when the temperature falls back below 110c, the regulator goes through the soft-start procedure again. the v tj pin is an accurate indicator of the internal silicon junction temperature t j , which can be determined by the following formula. this saves engineering time. where vtj is the voltage at vtj pin. under-voltage lockout (uvlo) when v dd falls bellow 2.5v, the regulator shuts down. when v dd rises above 2.8v, converter goes through soft-start process again. power good indicator (pg) and over-voltage protection when the output reaches 10% of the preset voltage, the pg pin outputs a hi signal as shown in the start-up waveform (figure 12). if the output voltage is higher than 10% of the preset value for any reason, pg will go low and the regulator will shut down. in addition to the indication power is good, the pg pin can be used for multiple regulators? start-up control as described in the next section. full start-up control the el7554 offers full start-up control. the core of this control is a start-up comparator in front of the main pwm controller. the stp and stn are the inputs to the comparator, whose hi output forces the pwm comparator to skip switching cycles. the us er can choose any of the following control configurations: 1. adjustable soft-start in this configuration, the ramp-up time is adjustable to any time longer than the building soft-start time of 2ms. the approximate ramp-up time, t st , is: figure 18 shows the waveforms. table 1. v o (v) r 1 (k )r 2 (k ) 0.8 2 open 12.4910 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 36 11.5 table 2. condition tm sel v o normal 0 x nominal high margin 1 1 nominal + 5% low margin 1 0 nominal - 5% v o v in r l r dson1 + () i o ? = v o 0.8 1 r 1 r 2 ------ - + ?? ?? ?? = el7554 c osc 100pf external sync source t j 75 1.2 v tj ? 0.00384 ------------------------ + = t st rc v o v in --------- ?? ?? ?? = el7554
11 fn7360.4 may 8, 2006 figure 21. adjustable start-up in this application, c in and c out may be increased to reduce input/output ripple because the pulse skipping nature of the method. 2. cascade start-up in this configuration, en pin of regulator 2 is connected to the pg pin of regulator 1 (figure 22). v o2 will only start after v o1 is good. figure 22. cascade start-up 3. linear start-up in the linear start-up tracking co nfiguration, the regulator with lower output voltage, v o2 , tracks the one with higher output voltage, v o1 . the waveform is shown in figure 19. figure 23. linear start-up tracking 4. offset start-up compared with the cascade start-up, this configuration allows regulator 2 to begin the start-up process when v o1 reaches a particular value of v ref *(1+r b /r a ) before pg goes hi, where v ref is the regulator reference voltage. v ref =1.26. figure 24. offset start-up tracking component selection input capacitor the main functions of the input capacitor(s) are to maintain the input voltage steady and to filter out the pulse current passing through the upper switch. the root-mean-square value of this current is: for a wide range of v in and v o . for long-term reliability, the input capacitor or combination of capacitors must have the current rating higher than i in,rms . use x5r or x7r type ceramic capacitors, or spcap or poscap types of polymer capaci tors for their high current handling capability. inductor the nfet positive current limit is set at about 5a. for optimal operation, the peak-to- peak inductor current ripple i l should be less than 1a. the following equation gives the inductance value: the peak current the inductor sees is: when inductor is chosen, make sure the inductor can handle this peak current and the average current of i o . output capacitor if there is no holding time re quirement for output; output voltage ripple and transient response are the main deciding factors in choosing the output ca pacitor. initially, choose the v in stp v o - + stn 0.1f 200k v o t st r c el7554 el7554 v in el7554 en pg v o2 v o1 v o2 v o1 v in stp v o1 - + stn c r - + v in v o2 v o1 v o2 el7554 el7554 v in v o1 - + v in v o2 v ref r b r a v o1 v o2 v ref (1+r b /r a ) el7554 el7554 i in,rms v o v in v o ? () v in ----------------------------------------------- i o 1/2 i ( o ) = l v in ( v o ) v o ? v in i l f s -------------------------------------------- = i lpk i o i l 2 -------- + = el7554
12 fn7360.4 may 8, 2006 output capacitor with the esr to satisfy the output ripple v o requirement: when output has a step load change i o , the initial voltage drop is esr* i o . then v o will drop even further before the loop has the chance to respond. the higher the output capacitance, the lower the voltage drop is. also, higher loop bandwidth will generate less voltage drop. experiment with the transient response (see figur e 15) to determine the final values of output capacitance. like the input capacitor, it is recommended to use x5r or x7r type of ceramic capacitors, or spcap or poscap type of polymer capacitors for the low esr and high capacitance. generally, the ac current rating of the output capacitor is not a concern because the rms current is only 1/ 12 of i l . this is easily satisfied. loop compensation current mode converter forces the inductor current proportional to the error signal, thus gets rid of the 2nd order effect formed by the inductor and output capacitor. the pwm comparator and the inductor form an equivalent transconductance amplifier. so, a simple type 1 compensator is good enough to generate a high bandwidth stable converter. the compensation capacitor and resister are decided by: where: ?gm pwm is the transconductance of the pwm comparator, gm pwm = 120s ?v out output voltage ?i out output current ?c out is output capacitance ?gm ea is the transconductance of the error amplifier, gm ea = 120s ?f c is the intended crossover frequency of the loop. for best performance, set this valu e to about one-tenth of the switching frequency. design example a 5v to 1.8v converter at 4a is needed. 1. choose the input capacitor the input capacitor or combinat ion of capacitors has to be able to take about 1/2 of the output current, e.g., 2a. tdk?s c3216x5ria106m is rated at 2.7a, 6.3v, meeting the above criteria using 2 generators less input voltage ripple. 2. choose the inductor. set the converter switching frequency at 600khz: i l = 1a yields 1.72h. leave some margin and choose l = 2.2h. tdk rlf7030-2r2m5r4 has the required current rating. 3. choose the output capacitor l = 2.2h yields about 0.9a inductor ripple current. 47f ceramic capacitor has less than 5m of esr easily satisfying by the requirement. esr is not the only factor deciding the output capacitance. as discussed earlier, output voltage droops less with more capacitance when converter is in load transient. multiple iterations may be needed before final components are chosen. 4. loop compensation 50khz is the intended crossover frequency. with the conditions r c and c c are calculated as: r c = 2.32k and c c = 0.018pf for convenience, table 3 lists the compensation values for frequently used output voltages. v o i l esr = c c v fb gm pwm gm ea f c i out ----------------------------------------------------------------- = r c 2r out c out c c --------------- - = r out v out i out --------------- - = table 3. compensation values v o (v) r c (k )c c (f) 3.3 4.22 0.018 2.5 3.24 0.018 1.8 2.32 0.018 1.5 1.91 0.018 1.2 1.54 0.018 1 1.27 0.018 0.8 1.02 0.018 l v in ( v o ) v o ? v in i l f s -------------------------------------------- = el7554
13 fn7360.4 may 8, 2006 thermal management the el7554ire is packaged in a thermally-efficient htssop-28 package, which utiliz es the exposed thermal pad at the bottom to spread heat through pcb metal. therefore: 1. the thermal pad must be soldered to the pcb 2. maximize the pcb area 3. if a multiple layer pcb is used, thermal vias (13 to 25 mil) must be placed underneath the thermal pad to connect to ground plane(s). do not place thermal reliefs on the vias. figure 25 shows a typical connection. the thermal resistance for this package is as low as 26c/w for 2 layer pcb of 0.39" thickness (see figure 9). the actual junction temperature can be measured at v tj pin. the thermal performance of the ic is heavily dependent on the layout of the pcb. the user should exercise care during the design phase to ensure the ic will operate within the recommended environmental conditions. figure 25. pcb layout - 28 ld htssop package layout considerations the layout is very important for the converter to function properly. follow these tips for best performance: 1. separate the power ground ( ) and signal ground ( ); connect them only at one po int right at the sgnd pin 2. place the input capacitor(s) as close to v in and pgnd pins as possible 3. make as small as possible the loop from lx pins to l to c o to pgnd pins 4. place r 1 and r 2 pins as close to the fb pin as possible 5. maximize the copper area around the pgnd pins; do not place thermal relief around them 6. thermal pad should be soldered to pcb. place several via holes under the chip to the ground plane to help heat dissipation the demo board is a good example of layout based on this outline. please refer to the el7554 application brief. ground plane connection component side connection el7554
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7360.4 may 8, 2006 package outline drawing note: the package drawing shown here may not be the latest version. to check the latest revision, please refer to the intersil w ebsite at http://www.intersil.com/design/packages/index.asp el7554

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